发明申请
- 专利标题: INFORMATION PROCESSING APPARATUS AND FALSIFICATION VERIFICATION METHOD
- 专利标题(中): 信息处理装置和伪造验证方法
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申请号: US12666636申请日: 2007-07-25
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公开(公告)号: US20110044451A1公开(公告)日: 2011-02-24
- 发明人: Jun Anzai , Hideki Matsushima , Tomoyuki Haga
- 申请人: Jun Anzai , Hideki Matsushima , Tomoyuki Haga
- 申请人地址: JP Kadoma-shi, Osaka
- 专利权人: PANASONIC CORPORATION
- 当前专利权人: PANASONIC CORPORATION
- 当前专利权人地址: JP Kadoma-shi, Osaka
- 国际申请: PCT/JP2007/064590 WO 20070725
- 主分类号: H04L9/12
- IPC分类号: H04L9/12 ; G06F12/00
摘要:
An object of the present invention is to provide an information processing apparatus in which a secure CPU and a non-secure CPU are included, that is capable of reliably detecting falsification of programs. The information processing apparatus according to the present invention includes a secure CPU 1, a non-secure CPU 2, a nonvolatile memory 3, a boot ROM 11, and a RAM 12. The secure CPU 1 verifies the presence or absence of falsification of various programs stored in the nonvolatile memory 3 with reference to a first falsification verification program stored in the boot ROM 11, according to a verification result, and loads a secure CPU target program 31 stored in the nonvolatile memory 3 into the RAM 12, and outputs a non-secure CPU target program stored in the nonvolatile memory 3 to the non-secure CPU 2 with reference to a load program loaded in the RAM 12.
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