Invention Application
US20110047524A1 SYSTEM AND METHOD FOR INSPECTING LAYOUT OF A PRINTED CIRCUIT BOARD
失效
用于检查印刷电路板布局的系统和方法
- Patent Title: SYSTEM AND METHOD FOR INSPECTING LAYOUT OF A PRINTED CIRCUIT BOARD
- Patent Title (中): 用于检查印刷电路板布局的系统和方法
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Application No.: US12701677Application Date: 2010-02-08
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Publication No.: US20110047524A1Publication Date: 2011-02-24
- Inventor: HSIEN-CHUAN LIANG , SHEN-CHUN LI , CHUN-JEN CHEN , SHOU-KUO HSU , DUEN-YI HO , YUNG-CHIEH CHEN
- Applicant: HSIEN-CHUAN LIANG , SHEN-CHUN LI , CHUN-JEN CHEN , SHOU-KUO HSU , DUEN-YI HO , YUNG-CHIEH CHEN
- Applicant Address: TW Tu-Cheng
- Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
- Current Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
- Current Assignee Address: TW Tu-Cheng
- Priority: CN200910305836.1 20090820
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A system and method for inspecting layout of a printed circuit board (PCB) provides a graphical user interface (GUI). The GUI displays a layout of the PCB. High side pins of a pulse width modulation (PWM) controller and a component connected to a high side pin are found. If the component is a metallic oxide semiconductor field effect transistor (MOSFET), the system calculate absolute a linear distance and a trace distance between a source pin of the MOSFET and a capacitor pin of a coupling capacitor connected to the source pin. If the linear distance, the trace distance and a capacitance of the coupling capacitor accord with a layout standard, the layout of the PCB is determined to be up to standard.
Public/Granted literature
- US08239815B2 System and method for inspecting layout of a printed circuit board Public/Granted day:2012-08-07
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