发明申请
US20110049637A1 BURIED ETCH STOP LAYER IN TRENCH ISOLATION STRUCTURES FOR SUPERIOR SURFACE PLANARITY IN DENSELY PACKED SEMICONDUCTOR DEVICES 有权
用于密封包装半导体器件中的超级表面平面的TRENCH隔离结构中的BURIED ETCH STOP LAY

BURIED ETCH STOP LAYER IN TRENCH ISOLATION STRUCTURES FOR SUPERIOR SURFACE PLANARITY IN DENSELY PACKED SEMICONDUCTOR DEVICES
摘要:
Material erosion of trench isolation structures in advanced semiconductor devices may be reduced by incorporating an appropriate mask layer stack in an early manufacturing stage. For example, a silicon nitride material may be incorporated as a buried etch stop layer prior to a sequence for patterning active regions and forming a strain-inducing semiconductor alloy therein, wherein, in particular, the corresponding cleaning process prior to the selective epitaxial growth process has been identified as a major source for causing deposition-related irregularities upon depositing the interlayer dielectric material.
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