发明申请
US20110049637A1 BURIED ETCH STOP LAYER IN TRENCH ISOLATION STRUCTURES FOR SUPERIOR SURFACE PLANARITY IN DENSELY PACKED SEMICONDUCTOR DEVICES
有权
用于密封包装半导体器件中的超级表面平面的TRENCH隔离结构中的BURIED ETCH STOP LAY
- 专利标题: BURIED ETCH STOP LAYER IN TRENCH ISOLATION STRUCTURES FOR SUPERIOR SURFACE PLANARITY IN DENSELY PACKED SEMICONDUCTOR DEVICES
- 专利标题(中): 用于密封包装半导体器件中的超级表面平面的TRENCH隔离结构中的BURIED ETCH STOP LAY
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申请号: US12858727申请日: 2010-08-18
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公开(公告)号: US20110049637A1公开(公告)日: 2011-03-03
- 发明人: Maciej Wiatr , Markus Forsberg , Stephan Kronholz , Roman Boschke
- 申请人: Maciej Wiatr , Markus Forsberg , Stephan Kronholz , Roman Boschke
- 优先权: DE102009039522.9 20090831
- 主分类号: H01L27/088
- IPC分类号: H01L27/088 ; H01L21/8234
摘要:
Material erosion of trench isolation structures in advanced semiconductor devices may be reduced by incorporating an appropriate mask layer stack in an early manufacturing stage. For example, a silicon nitride material may be incorporated as a buried etch stop layer prior to a sequence for patterning active regions and forming a strain-inducing semiconductor alloy therein, wherein, in particular, the corresponding cleaning process prior to the selective epitaxial growth process has been identified as a major source for causing deposition-related irregularities upon depositing the interlayer dielectric material.