Invention Application
- Patent Title: PACKAGE SUBSTRATE
- Patent Title (中): 包装基板
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Application No.: US12614411Application Date: 2009-11-07
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Publication No.: US20110067901A1Publication Date: 2011-03-24
- Inventor: Jin Ho KIM , Seok Kyu LEE , Jae Joon LEE , Sung Won JEONG
- Applicant: Jin Ho KIM , Seok Kyu LEE , Jae Joon LEE , Sung Won JEONG
- Priority: KR10-2009-0090098 20090923
- Main IPC: H05K1/00
- IPC: H05K1/00

Abstract:
Disclosed is a package substrate, in which the plating area of a first plating layer formed on a layer which is to be connected to a motherboard is larger than the plating area of a second plating layer formed on a layer which is to be connected to an electronic part, and open portions are formed on the first plating layer, thus balancing the plating areas of the plating layers formed on the layers of the package substrate, thereby minimizing warpage of the package substrate due to differing coefficients of thermal expansion.
Information query