Invention Application
US20110067901A1 PACKAGE SUBSTRATE 审中-公开
包装基板

PACKAGE SUBSTRATE
Abstract:
Disclosed is a package substrate, in which the plating area of a first plating layer formed on a layer which is to be connected to a motherboard is larger than the plating area of a second plating layer formed on a layer which is to be connected to an electronic part, and open portions are formed on the first plating layer, thus balancing the plating areas of the plating layers formed on the layers of the package substrate, thereby minimizing warpage of the package substrate due to differing coefficients of thermal expansion.
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