发明申请
US20110078540A1 INTERLACED ITERATIVE SYSTEM DESIGN FOR 1K-BYTE BLOCK WITH 512-BYTE LDPC CODEWORDS 有权
具有512位LDPC编码器的1K字节块的互连迭代系统设计

INTERLACED ITERATIVE SYSTEM DESIGN FOR 1K-BYTE BLOCK WITH 512-BYTE LDPC CODEWORDS
摘要:
To allow a single LDPC decoder to operate on both 512 B blocks and 4 KB blocks with comparable error correction performance, 512 KB blocks are interlaced to form a 1 KB data sequence, and four sequential 1 KB data sequences are concatenated to form a 4 KB sector. A de-interlacer between the detector and decoder forms multiple data sequence from a single data sequence output by the detector. The multiple data sequences are separately processed by a de-interleaver between the de-interlacer and the LDPC decoder, by the LDPC decoder, and by an interleaver at the output of the LDPD decoder. An interlacer recombines the multiple data sequences into a single output. Diversity may be improved by feeding interleaver seeds for respective codewords into the de-interleaver and interleaver during processing.
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