发明申请
- 专利标题： WORDLINE RESISTANCE REDUCTION METHOD AND STRUCTURE IN AN INTEGRATED CIRCUIT MEMORY DEVICE
- 专利标题（中）： 集成电路存储器件中的电阻降低方法和结构
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申请号： US12961379申请日： 2010-12-06
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公开(公告)号： US20110095370A1公开(公告)日： 2011-04-28
- 发明人: Shenqing FANG , Jihwan CHOI , Connie WANG , Eunha KIM
- 申请人： Shenqing FANG , Jihwan CHOI , Connie WANG , Eunha KIM
- 主分类号： H01L29/78
- IPC分类号： H01L29/78
摘要：
Methods and structures for reducing resistance in wordlines of an integrated circuit memory device are disclosed. In one embodiment, the method includes forming multiple columns of polycrystalline silicon for respective number of wordlines, forming core transistor junctions and periphery transistor junctions associated with the wordlines, performing a salicidation process for the periphery transistor junction and performing a salicidation process for the columns of polycrystalline silicon to from the wordlines with low resistance.
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