发明申请
- 专利标题: MASK LEVEL REDUCTION FOR MOFET
- 专利标题(中): 屏蔽层减少MOFET
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申请号: US12612123申请日: 2009-11-04
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公开(公告)号: US20110104841A1公开(公告)日: 2011-05-05
- 发明人: Chan-Long Shieh , Fatt Foong , Gang Yu
- 申请人: Chan-Long Shieh , Fatt Foong , Gang Yu
- 主分类号: H01L21/8234
- IPC分类号: H01L21/8234 ; H01L21/8254 ; H01L33/00
摘要:
A method of fabricating a thin film transistor for an active matrix display using reduced masking operations includes patterning a gate on a substrate. A gate dielectric is formed over the gate and a semiconducting metal oxide is deposited on the gate dielectric. A channel protection layer is patterned on the semiconducting metal oxide overlying the gate to define a channel area and to expose the remaining semiconducting metal oxide. A source/drain metal layer is deposited on the structure and etched through to the channel protection layer above the gate to separate the source/drain metal layer into source and drain terminals and the source/drain metal layer and the semiconducting metal oxide are etched through at the periphery to isolate the transistor. A nonconductive spacer is patterned on the transistor and portions of the surrounding source/drain metal layer.
公开/授权文献
- US08187929B2 Mask level reduction for MOSFET 公开/授权日:2012-05-29
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