A hardware pipeline has a number of rows including a first row, a last row, and an intermediate row between the first row and the last row. Each row stores a number of bytes of data as the data moves through the pipeline on a row-by-row basis from the first row towards the last row. A mechanism performs a first macro on the data beginning at the first row. The mechanism performs a second macro different than the first macro on the data beginning at the intermediate row where the first macro has been completely performed when the data has reached the intermediate row. The first and second macros each include a number of modifications of the data as the data moves through the pipeline to effect a complete transformation of the data. The complete transformation of the first macro is different than the complete transformation of the second data.