发明申请
- 专利标题: GRAPHICS RENDER CLOCK THROTTLING AND GATING MECHANISM FOR POWER SAVING
- 专利标题(中): 图形渲染时钟节流和节能机制
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申请号: US12908308申请日: 2010-10-20
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公开(公告)号: US20110148887A1公开(公告)日: 2011-06-23
- 发明人: Lai Kuan Chong , Lai Guan Tang
- 申请人: Lai Kuan Chong , Lai Guan Tang
- 优先权: MYPI20095512 20091222
- 主分类号: G06T1/00
- IPC分类号: G06T1/00
摘要:
An example of a controller circuit may include a policy module to generate a power reduction policy output based on a processor power state input. The power reduction policy output may also be generated based on a graphics render engine idleness input. The circuit can also include a clock masking cell to apply a clock masking configuration to a graphics render clock trunk based on the power reduction policy output.
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