发明申请
US20110154273A1 METHOD OF GENERATING MASK PATTERN, MASK PATTERN GENERATING PROGRAM, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
审中-公开
生成掩模图案，掩模图案生成程序的方法和制造半导体器件的方法
- 专利标题： METHOD OF GENERATING MASK PATTERN, MASK PATTERN GENERATING PROGRAM, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
- 专利标题（中）： 生成掩模图案，掩模图案生成程序的方法和制造半导体器件的方法
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申请号： US12964185申请日： 2010-12-09
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公开(公告)号： US20110154273A1公开(公告)日： 2011-06-23
- 发明人: Ryota ABURADA , Toshiya Kotani
- 申请人： Ryota ABURADA , Toshiya Kotani
- 优先权： JP2009-287716 20091218
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
According to one embodiment, in process simulation, it is verified whether sidewall patterns formed on sidewalls of a core material pattern or a transfer pattern formed by transferring the core material pattern form a closed loop. When it is determined as a result of the verification that the sidewall patterns form a closed loop, the mask pattern is changed. When it is determined as a result of the verification that the sidewall patterns do not form a closed loop, the mask pattern is adopted.
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