发明申请
- 专利标题： Controlling Depth and Latency of Exit of a Virtual Processor's Idle State in a Power Management Environment
- 专利标题（中）： 控制电源管理环境中虚拟处理器空闲状态退出的深度和延迟
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申请号： US12645597申请日： 2009-12-23
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公开(公告)号： US20110154323A1公开(公告)日： 2011-06-23
- 发明人: Richard L. Arndt , Naresh Nayar , Christopher Francois , Karthick Rajamani , Freeman L. Rawson, III , Randal C. Swanberg
- 申请人： Richard L. Arndt , Naresh Nayar , Christopher Francois , Karthick Rajamani , Freeman L. Rawson, III , Randal C. Swanberg
- 申请人地址： US NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： US NY Armonk
- 主分类号： G06F9/455
- IPC分类号： G06F9/455
摘要：
A mechanism is provided in a logically partitioned data processing system for controlling depth and latency of exit of a virtual processor's idle state. A virtualization layer generates a cede latency setting information (CLSI) data. Responsive to booting a logical partition, the virtualization layer communicates the CLSI data to an operating system (OS) of the logical partition. The OS determines, based on the CLSI data, a particular idle state of a virtual processor under a control of the OS. Responsive to the OS calling the virtualization layer, the OS communicates the particular idle state of the virtual processor to the virtualization layer for assigning the particular idle state and wake-up characteristics to the virtual processor.
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