发明申请
- 专利标题： LOW LATENCY SERIAL MEMORY INTERFACE
- 专利标题（中）： 低延迟串行存储器接口
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申请号： US12648373申请日： 2009-12-29
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公开(公告)号： US20110161544A1公开(公告)日： 2011-06-30
- 发明人: David P. Chengson , Chang-Hong Wu
- 申请人： David P. Chengson , Chang-Hong Wu
- 申请人地址： US CA Sunnyvale
- 专利权人： JUNIPER NETWORKS, INC.
- 当前专利权人： JUNIPER NETWORKS, INC.
- 当前专利权人地址： US CA Sunnyvale
- 主分类号： G06F13/14
- IPC分类号： G06F13/14 ; G06F13/00 ; G06F1/04
摘要：
A device applies synchronous clocking across a first component and a second component of the device, and designates a particular serial link, from a group of serial links, as a master serial link. The device also designates the remaining serial links as slave serial links, provides, via the master serial link, an encoded data stream, and provides, via the slave serial links, un-encoded and scrambled data streams.
公开/授权文献
- US08452908B2 Low latency serial memory interface 公开/授权日：2013-05-28
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