发明申请
- 专利标题: ERROR CONTROLLING SYSTEM, PROCESSOR AND ERROR INJECTION METHOD
- 专利标题(中): 错误控制系统,处理器和错误注入方法
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申请号: US12974336申请日: 2010-12-21
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公开(公告)号: US20110161747A1公开(公告)日: 2011-06-30
- 发明人: Iwao YAMAZAKI
- 申请人: Iwao YAMAZAKI
- 申请人地址: JP Kawasaki
- 专利权人: FUJITSU LIMITED
- 当前专利权人: FUJITSU LIMITED
- 当前专利权人地址: JP Kawasaki
- 优先权: JP2009-296260 20091225
- 主分类号: G06F11/00
- IPC分类号: G06F11/00
摘要:
An error controlling system includes a plurality of error generation target circuits, a plurality of pseudo error generating devices each having a pseudo error content holding register that holds directed pseudo error content, each plurality of pseudo error generating device generates a pseudo error corresponding to a pseudo error content held in a respective pseudo error content holding register in at least one of data to be written to one of the plurality of error generation target circuits and data to be read from one of the plurality of error generation target circuits upon being directed to generate the pseudo error, and a pseudo error controlling device that directs the plurality of pseudo error generating devices to generate a pseudo error corresponding to a respective pseudo error content held in each of the pseudo error content holding register provided in each of the plurality of pseudo error generating devices.
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