发明申请
US20110167211A1 DRAM CONTROLLER FOR VIDEO SIGNAL PROCESSING OPERABLE TO ENABLE/DISABLE BURST TRANSFER
审中-公开
用于视频信号处理的DRAM控制器可用于启用/禁用BURST传输
- 专利标题： DRAM CONTROLLER FOR VIDEO SIGNAL PROCESSING OPERABLE TO ENABLE/DISABLE BURST TRANSFER
- 专利标题（中）： 用于视频信号处理的DRAM控制器可用于启用/禁用BURST传输
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申请号： US13049293申请日： 2011-03-16
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公开(公告)号： US20110167211A1公开(公告)日： 2011-07-07
- 发明人: Masanori HENMI , Kazushi Kurata
- 申请人： Masanori HENMI , Kazushi Kurata
- 申请人地址： JP Osaka
- 专利权人： PANASONIC CORPORATION
- 当前专利权人： PANASONIC CORPORATION
- 当前专利权人地址： JP Osaka
- 优先权： JP2004-002275 20040107
- 主分类号： G06F12/06
- IPC分类号： G06F12/06
摘要：
An interface unit 20 assigns different SDRAMs 1 and 2 to adjacent drawing blocks in a frame-buffer area. In processing that extends across the adjacent drawing blocks, active commands, for example, are issued alternately to the SDRAMs 1 and 2 to reduce waiting cycles resulting from the issue interval restriction. Furthermore, since individual clock enable signals CKE1 and CKE2 are output to the SDRAMs 1 and 2 so that burst transfers of the SDRAMs 1 and 2 can be stopped individually, no cycle is necessary to stop the burst transfers.
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