A stacked electrostatic discharge (ESD) protection clamp (99, 100-104) for protecting associated devices or circuits (24) comprises two or more series coupled (stacked) bipolar transistors (70, 700) whose individual trigger voltages Vt1 depend on their base-collector spacing D. A first (70-1, 700-1) of the transistors (70, 700) has a spacing DZ1 chosen within a D range Z1 whose slope (ΔVt1/ΔD) has a first value (ΔVt1/ΔD)Z1, and a second (70-2, 700-2) of the transistors (70, 700) has a spacing value D(Z2 or Z3) chosen within a D range Z2 or Z3 whose slope (ΔVt1/ΔD) has a second value (ΔVt1/ΔD)(Z2 or Z3) less than the first value (ΔVt1/ΔD)Z1. The sensitivity of the ESD stack trigger voltage Vt1STACK to base-collector spacing variations ΔD during manufacture is much reduced, for example, by as much as 50% for a 2-stack and more for 3-stacks and beyond. A wide range of Vt1STACK values can be obtained that are less sensitive to unavoidable manufacturing spacing variations ΔD.