发明申请
US20110185331A1 Reducing Voltage Drops in Power Networks Using Unused Spaces in Integrated Circuits 有权
降低集成电路中未使用空间的电力网络中的电压降

Reducing Voltage Drops in Power Networks Using Unused Spaces in Integrated Circuits
摘要:
A method of designing an integrated circuit includes providing an integrated circuit design including a power network. A voltage drop mitigation system is provided, which includes a power strap enhancer configured to automatically find a source node and a terminal node in the power network. A redundant strap for the power network using the voltage drop mitigation system is added, wherein the redundant strap interconnects the source node and the terminal node. After the step of adding the redundant strap, dummy patterns may be added.
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