发明申请
US20110196905A1 STORING DATA TO MULTI-CHIP LOW-LATENCY RANDOM READ MEMORY DEVICE USING NON-ALIGNED STRIPING
有权
将数据存储到使用非对齐条带的多芯片低延迟读取存储器件
- 专利标题： STORING DATA TO MULTI-CHIP LOW-LATENCY RANDOM READ MEMORY DEVICE USING NON-ALIGNED STRIPING
- 专利标题（中）： 将数据存储到使用非对齐条带的多芯片低延迟读取存储器件
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申请号： US13087710申请日： 2011-04-15
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公开(公告)号： US20110196905A1公开(公告)日： 2011-08-11
- 发明人: Jeffrey S. Kimmel , Rajesh Sundaram , George Totolos, JR. , Michael W.J. Hordijk
- 申请人： Jeffrey S. Kimmel , Rajesh Sundaram , George Totolos, JR. , Michael W.J. Hordijk
- 主分类号： G06F17/30
- IPC分类号： G06F17/30
摘要：
Described herein are method and apparatus for storing data to a low-latency random read memory (LLRRM) device using non-aligned data striping, the LLRRM device being implemented on a storage system. The LLRRM device may comprise a bank comprising a plurality of memory chips, each chip being simultaneously accessible for storing data on a plurality of erase-units (EUs). A storage operating system may maintain, for each chip, a reserve data structure listing reserve EUs and a remapping data structure for tracking remappings between defective EUs to reserve EUs in the chip. A defective EU in a chip may be mapped to a reserve EU from the reserve data structure. Upon receiving a data block to be stored to the LLRRM device at the defective EU, the storage operating system may stripe the received data block across a plurality of chips in a non-aligned manner using the remapped reserve EU.
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