发明申请
- 专利标题: Mixed Concurrent And Serial Logic Simulation Of Hardware Designs
- 专利标题(中): 混合并行和串行逻辑仿真硬件设计
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申请号: US13031139申请日: 2011-02-18
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公开(公告)号: US20110218792A1公开(公告)日: 2011-09-08
- 发明人: Keith Whisnant , Claudio Basile , Giacinto Paolo Saggese
- 申请人: Keith Whisnant , Claudio Basile , Giacinto Paolo Saggese
- 申请人地址: US CA Mountain View
- 专利权人: Synopsys, Inc.
- 当前专利权人: Synopsys, Inc.
- 当前专利权人地址: US CA Mountain View
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
A method of simulating a design described in HDL is provided. In this method, modules of the design can be partitioned into first modules for simulation by a serial simulation engine and second modules for simulation by a concurrent simulation engine. The first and second modules can be prioritized for simulation based on classes of events consistent with an execution model of the HDL. Simulations of the serial and concurrent simulation engines can be synchronized for each class of events. Synchronizing can include transferring updated interface variable values, which are shared by the second modules and at least a subset of the first modules, between the serial simulation engine and the concurrent simulation engine. This transferring can include translating representations of the updated interface variable values.
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