发明申请
- 专利标题： Layered chip package with wiring on the side surfaces
- 专利标题（中）： 分层芯片封装，侧面布线
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申请号： US13067195申请日： 2011-05-16
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公开(公告)号： US20110221073A1公开(公告)日： 2011-09-15
- 发明人: Yoshitaka Sasaki , Hiroyuki Ito , Tatsuya Harada , Nobuyuki Okuzawa , Satoru Sueki , Hiroshi Ikejima
- 申请人： Yoshitaka Sasaki , Hiroyuki Ito , Tatsuya Harada , Nobuyuki Okuzawa , Satoru Sueki , Hiroshi Ikejima
- 申请人地址： US CA Milpitas CN Hong Kong JP Tokyo
- 专利权人： HEADWAY TECHNOLOGIES, INC.,SAE MAGNETICS (H.K.) LTD.,TDK CORPORATION
- 当前专利权人： HEADWAY TECHNOLOGIES, INC.,SAE MAGNETICS (H.K.) LTD.,TDK CORPORATION
- 当前专利权人地址： US CA Milpitas CN Hong Kong JP Tokyo
- 主分类号： H01L23/538
- IPC分类号： H01L23/538
摘要：
A layered chip package has a main body including pairs of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip. The pairs of layer portions include specific pairs of layer portions. Each of the specific pairs of layer portions includes a first-type layer portion and a second-type layer portion. The first-type layer portion includes electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the second-type layer portion does not include such electrodes. The specific pairs of layer portions are provided in an even number.
公开/授权文献
- US08324741B2 Layered chip package with wiring on the side surfaces 公开/授权日：2012-12-04
信息查询
IPC分类:
