发明申请
- 专利标题: ECHO CANCELLATION CIRCUIT
- 专利标题(中): ECHO CANCELLATION电路
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申请号: US13044346申请日: 2011-03-09
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公开(公告)号: US20110222446A1公开(公告)日: 2011-09-15
- 发明人: Shinji Nakatsuka , Kazuhiro Oda
- 申请人: Shinji Nakatsuka , Kazuhiro Oda
- 申请人地址: JP Tokyo
- 专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人地址: JP Tokyo
- 优先权: JPJP2010-057922 20100315; JPJP2010-057923 20100315
- 主分类号: H04B3/20
- IPC分类号: H04B3/20
摘要:
An echo cancellation circuit in a full duplex two-way communication system comprising: an input/output terminal; a subtractor having a positive and a negative input terminals, in which a first transmission signal is inputted to the negative input terminal as a pseudo echo signal, the first transmission signal is inputted through an output buffer to the positive input terminal as an echo signal, the pseudo echo signal inputted to the negative input terminal is subtracted from the echo signal inputted to the positive input terminal; and a result of the subtraction is outputted; and an echo cancellation error reducing unit having a D/A converter at an input side or an output side of the subtractor.
公开/授权文献
- US08526339B2 Echo cancellation circuit 公开/授权日:2013-09-03
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