发明申请
US20110231719A1 Logic Built-In Self-Test Programmable Pattern Bit Mask 失效
逻辑内置自检可编程模式位掩码

Logic Built-In Self-Test Programmable Pattern Bit Mask
摘要:
In a particular embodiment, a method is disclosed that includes mapping failing bit positions within multiple scan chains to memory locations of a memory mask. The method also includes executing logic built-in self-test (LBIST) testing on a semiconductor device using the memory mask to selectively mask certain results within the multiple scan chains. The results are associated with performance of LBIST testing on the semiconductor device.
公开/授权文献
信息查询
0/0