发明申请
- 专利标题： CHIP PACKAGE
- 专利标题（中）： 芯片包装
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申请号： US13173255申请日： 2011-06-30
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公开(公告)号： US20110260327A1公开(公告)日： 2011-10-27
- 发明人: Ming-Chiang Lee
- 申请人： Ming-Chiang Lee
- 申请人地址： TW Kaohsiung
- 专利权人： ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- 当前专利权人： ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- 当前专利权人地址： TW Kaohsiung
- 优先权： TW97147881 20081209
- 主分类号： H01L23/48
- IPC分类号： H01L23/48
摘要：
A quad flat non-leaded package including a first patterned conductive layer, a second patterned conductive layer, a chip, bonding wires and a molding compound is provided. The first patterned conductive layer defines a first space, and the second patterned conductive layer defines a second space, wherein the first space overlaps the second space and a part of the second patterned conductive layer surrounding the second space. The chip is disposed on the second patterned conductive layer. The bonding wires are connected between the chip and the second patterned conductive layer. The molding compound encapsulates the second patterned conductive layers, the chip and the bonding wires. In addition, a method of manufacturing a quad flat non-leaded package is also provided.
公开/授权文献
- US08497585B2 Chip package 公开/授权日：2013-07-30
信息查询
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