发明申请
- 专利标题： MICROPROCESSOR ARCHITECTURE AND METHOD OF INSTRUCTION DECODING
- 专利标题（中）： 微处理器架构和指令解码方法
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申请号： US13142431申请日： 2009-01-21
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公开(公告)号： US20110271083A1公开(公告)日： 2011-11-03
- 发明人: Martin Raubuch , Norbert Stoeffler
- 申请人： Martin Raubuch , Norbert Stoeffler
- 申请人地址： US TX AUSTIN
- 专利权人： FREESCALE SEMICONDUCTOR, INC.
- 当前专利权人： FREESCALE SEMICONDUCTOR, INC.
- 当前专利权人地址： US TX AUSTIN
- 国际申请： PCT/IB09/50215 WO 20090121
- 主分类号： G06F9/30
- IPC分类号： G06F9/30
摘要：
A microprocessor architecture comprises an instruction decoding network for decoding in a first mode partially suppressed opcodes of a sequence of instructions, the opcodes comprising a first part containing parameters being invariant for each opcode of the sequence and a second part comprising a flag indicating an end of the sequence, the first part being suppressed for all opcodes of the sequence except a first opcode of the sequence. Further, a method of instruction decoding in a microprocessor architecture comprising an instruction decoding network for decoding in a first mode partially suppressed opcodes of a sequence of instructions, and in a second mode uncompressed instructions comprises decoding an opcode of an instruction in the second mode when the instruction is not compressible; and decoding an opcode of an instruction in the first mode when the instruction is compressible.