发明申请
US20110299354A1 MEMORY ARRAY CIRCUIT INCORPORATING MULTIPLE ARRAY BLOCK SELECTION AND RELATED METHOD 有权
包含多个阵列块选择的存储阵列电路及相关方法

  • 专利标题: MEMORY ARRAY CIRCUIT INCORPORATING MULTIPLE ARRAY BLOCK SELECTION AND RELATED METHOD
  • 专利标题(中): 包含多个阵列块选择的存储阵列电路及相关方法
  • 申请号: US13215134
    申请日: 2011-08-22
  • 公开(公告)号: US20110299354A1
    公开(公告)日: 2011-12-08
  • 发明人: Roy E. ScheuerleinLuca G. Fasoli
  • 申请人: Roy E. ScheuerleinLuca G. Fasoli
  • 主分类号: G11C8/00
  • IPC分类号: G11C8/00
MEMORY ARRAY CIRCUIT INCORPORATING MULTIPLE ARRAY BLOCK SELECTION AND RELATED METHOD
摘要:
Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
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