发明申请
US20110317478A1 Method and Circuit Arrangement for Performing a Write Through Operation, and SRAM Array With Write Through Capability
审中-公开
用于执行写入操作的方法和电路布置，以及具有写入能力的SRAM阵列
- 专利标题： Method and Circuit Arrangement for Performing a Write Through Operation, and SRAM Array With Write Through Capability
- 专利标题（中）： 用于执行写入操作的方法和电路布置，以及具有写入能力的SRAM阵列
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申请号： US13150458申请日： 2011-06-01
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公开(公告)号： US20110317478A1公开(公告)日： 2011-12-29
- 发明人: Yuen H. Chan , Michael Kugel , Antonio Pelella , Tobias Werner
- 申请人： Yuen H. Chan , Michael Kugel , Antonio Pelella , Tobias Werner
- 申请人地址： US NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： US NY Armonk
- 优先权： EP10167274.9 20100625
- 主分类号： G11C11/34
- IPC分类号： G11C11/34 ; G11C11/00
摘要：
An improved method for performing a write through operation during a write operation of a SRAM cell (10) of a SRAM array (1) is disclosed. The method comprises suppressing a false write through data propagation at an output node (C, F) of the SRAM array (1) in case of a failure causing transition at a first node (t) or a second node (c) of the SRAM cell (10) by using information about the input data (data, data_b) to be written in the SRAM cell (10) and read data propagation paths to retain the output node (C, F) after a global bit line (gb_t, gb_c) at a precharge level independently from a logical level of the global bit line (gb_t, gb_c), if a corresponding node (c, t) of the SRAM cell (10) is performing the failure causing transition based on input data (data, data_b) to be written in the SRAM cell (10).
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