发明申请
US20110320997A1 Delay-Cell Footprint-Compatible Buffers 审中-公开
延迟单元脚印兼容缓冲区

Delay-Cell Footprint-Compatible Buffers
摘要:
A method for creating a design for an integrated circuit, by developing a set of delay cells where each of the cells in the set has a different delay time from the other cells in the set, and where each of the cells in the set has the same surface area, has the same pin-outs, has the same drive strength, and has the same input capacitance, where an originally-used cell in the set can be swapped out for a different replacement cell in the set without any impact on the design of the integrated circuit besides a change in delay time from the originally-used cell to the replacement cell.
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