Invention Application
- Patent Title: MEMORY MODULE AND LAYOUT METHOD THEREFOR
- Patent Title (中): 存储器模块和布局方法
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Application No.: US13270587Application Date: 2011-10-11
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Publication No.: US20120026772A1Publication Date: 2012-02-02
- Inventor: Shiro Harashima , Wataru Tsukada
- Applicant: Shiro Harashima , Wataru Tsukada
- Applicant Address: JP Tokyo
- Assignee: Elpida Memory, Inc.
- Current Assignee: Elpida Memory, Inc.
- Current Assignee Address: JP Tokyo
- Priority: JP2008-328224 20081224
- Main IPC: G11C5/02
- IPC: G11C5/02
Abstract:
The present invention provides a novel wiring method for LR-DIMM of VLP type that conforms to LR-DIMM technology. The LR-DIMM comprises a plurality of DRAMs mounted on a board, two connectors mounted on the board for receiving data, and a buffer device mounted on the board for redriving data applied to the two connectors to supply the data to the plurality of DRAMs. The buffer device is located near the center of the board on which the two connectors are arranged at both ends thereof, and supplies data from each connector to DRAMs arranged on the opposite side to the connector.
Public/Granted literature
- US08243488B2 Memory module and layout method therefor Public/Granted day:2012-08-14
Information query
