Invention Application
- Patent Title: METHOD FOR INTEGRATING DRAM AND NVM
- Patent Title (中): 集成DRAM和NVM的方法
-
Application No.: US12853450Application Date: 2010-08-10
-
Publication No.: US20120040504A1Publication Date: 2012-02-16
- Inventor: HSIN CHANG LIN , CHIA-HAO TAI , YANG-SEN YEN , MING-TSANG YANG , YA-TING FAN
- Applicant: HSIN CHANG LIN , CHIA-HAO TAI , YANG-SEN YEN , MING-TSANG YANG , YA-TING FAN
- Applicant Address: TW HSINCHU COUNTY
- Assignee: YIELD MICROELECTRONICS CORP.
- Current Assignee: YIELD MICROELECTRONICS CORP.
- Current Assignee Address: TW HSINCHU COUNTY
- Main IPC: H01L21/8246
- IPC: H01L21/8246

Abstract:
The present invention discloses a method for integrating DRAM and NVM, which comprises steps: sequentially forming on a portion of surface of a DRAM semiconductor substrate a first gate insulation layer and a first gate layer functioning as a floating gate; and implanting ion into regions of the semiconductor substrate, which are at two sides of the first gate insulation layer, to form two heavily-doped areas that are adjacent to the first gate insulation layer and respectively function as a drain and a source; respectively forming over the first gate layer a second gate insulation layer and a second gate layer functioning as a control gate. The present invention not only increases the transmission speed but also reduces the power consumption, the fabrication cost and the package cost.
Information query
IPC分类: