Invention Application
- Patent Title: CIRCUIT FOR SIMULTANEOUSLY ANALYZING PERFORMANCE AND BUGS AND METHOD THEREOF
- Patent Title (中): 同时分析性能和电阻的电路及其方法
-
Application No.: US13233008Application Date: 2011-09-14
-
Publication No.: US20120079161A1Publication Date: 2012-03-29
- Inventor: Hsuan-Ching Chao , Cheng-Pin Huang , Yu-Chiun Lin , Chia-Chun Chiang
- Applicant: Hsuan-Ching Chao , Cheng-Pin Huang , Yu-Chiun Lin , Chia-Chun Chiang
- Main IPC: G06F13/36
- IPC: G06F13/36
Abstract:
A circuit for simultaneously analyzing performance and bugs includes a mapping unit and a USB 3.0 data flow analyzer. The mapping unit is used for mapping commands transmitted to a USB 3.0 host through a peripheral component interconnect express and internal events of the USB 3.0 host to a packet of a USB 3.0 bus. The USB 3.0 data flow analyzer is used for analyzing performance and bugs of the USB 3.0 host through the packet of the USB 3.0 bus.
Public/Granted literature
- US08566501B2 Circuit for simultaneously analyzing performance and bugs and method thereof Public/Granted day:2013-10-22
Information query
