Invention Application
- Patent Title: VERTICAL TRANSISTOR AND METHOD FOR FORMING THE SAME
- Patent Title (中): 垂直晶体管及其形成方法
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Application No.: US13314532Application Date: 2011-12-08
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Publication No.: US20120080745A1Publication Date: 2012-04-05
- Inventor: Eun Sung LEE
- Applicant: Eun Sung LEE
- Applicant Address: KR Gyeonggi-do
- Assignee: HYNIX SEMICONDUCTOR INC.
- Current Assignee: HYNIX SEMICONDUCTOR INC.
- Current Assignee Address: KR Gyeonggi-do
- Priority: KR10-2008-0000313 20080102
- Main IPC: H01L29/78
- IPC: H01L29/78
Abstract:
A vertical transistor includes a semiconductor substrate provided with a pillar type active pattern over the surface thereof. A first tensile layer is formed over the semiconductor substrate and around the lower end portion of the pillar type active pattern, and a second tensile layer is formed over the upper end portion of the pillar type active pattern so that a tensile stress is applied in a vertical direction to the pillar type active pattern. A first junction region is formed within the surface of the semiconductor substrate below the first tensile layer and the pillar type active pattern. A gate is formed so as to surround at least a portion of the pillar type active pattern. A second junction region is formed within the upper end portion of the pillar type active pattern.
Public/Granted literature
- US08569832B2 Vertical transistor having first and second tensile layers Public/Granted day:2013-10-29
Information query
IPC分类:
