Invention Application
US20120089958A1 Apparatus and Methods for Optimizing the Performance of Programmable Logic Devices
审中-公开
用于优化可编程逻辑器件性能的装置和方法
- Patent Title: Apparatus and Methods for Optimizing the Performance of Programmable Logic Devices
- Patent Title (中): 用于优化可编程逻辑器件性能的装置和方法
-
Application No.: US13326082Application Date: 2011-12-14
-
Publication No.: US20120089958A1Publication Date: 2012-04-12
- Inventor: David Lewis , Vaughn Betz , Paul Leventis , Christopher Lane , Andy Lee , Jeffrey Watt , Timothy Vanderhoek
- Applicant: David Lewis , Vaughn Betz , Paul Leventis , Christopher Lane , Andy Lee , Jeffrey Watt , Timothy Vanderhoek
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
A programmable logic device (PLD) includes first and second circuits. The first and second circuits are part of a user's design to be implemented using the PLD's resources. The first circuit is powered by a first supply voltage. The second circuit is powered by a second supply voltage. At least one of the first and second supply voltages is determined by a PLD computer-aided design (CAD) flow used to implement the user's design in the PLD.
Information query
