发明申请
US20120089958A1 Apparatus and Methods for Optimizing the Performance of Programmable Logic Devices
审中-公开
用于优化可编程逻辑器件性能的装置和方法
- 专利标题： Apparatus and Methods for Optimizing the Performance of Programmable Logic Devices
- 专利标题（中）： 用于优化可编程逻辑器件性能的装置和方法
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申请号： US13326082申请日： 2011-12-14
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公开(公告)号： US20120089958A1公开(公告)日： 2012-04-12
- 发明人: David Lewis , Vaughn Betz , Paul Leventis , Christopher Lane , Andy Lee , Jeffrey Watt , Timothy Vanderhoek
- 申请人： David Lewis , Vaughn Betz , Paul Leventis , Christopher Lane , Andy Lee , Jeffrey Watt , Timothy Vanderhoek
- 专利权人： Altera Corporation
- 当前专利权人： Altera Corporation
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
A programmable logic device (PLD) includes first and second circuits. The first and second circuits are part of a user's design to be implemented using the PLD's resources. The first circuit is powered by a first supply voltage. The second circuit is powered by a second supply voltage. At least one of the first and second supply voltages is determined by a PLD computer-aided design (CAD) flow used to implement the user's design in the PLD.
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