Invention Application
US20120098557A1 CAPACITIVE INPUT TEST METHOD 有权
电容式输入测试方法

CAPACITIVE INPUT TEST METHOD
Abstract:
Method and system are provided for evaluating linearity of a capacitive-to-digital converter (CDC) of a capacitive sensor integrated circuit chip. The evaluating employs multiple test capacitors, which may be on-chip with the CDC, and includes: obtaining capacitance values for the multiple test capacitors and parasitic capacitances of a first input A and a second input B to the capacitive-to-digital converter; applying the multiple test capacitors in multiple permutations to the first input A and the second input B, and for each of at least some permutations, determining an error between an expected output of the CDC using the obtained capacitance values and an actual measured output of the CDC; and determining linearity error for the CDC using the determined errors for the permutations of applying the multiple test capacitors to the first input A and the second input B of the CDC.
Public/Granted literature
Information query
Patent Agency Ranking
0/0