Invention Application
- Patent Title: CAPACITIVE INPUT TEST METHOD
- Patent Title (中): 电容式输入测试方法
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Application No.: US13144036Application Date: 2010-01-12
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Publication No.: US20120098557A1Publication Date: 2012-04-26
- Inventor: Mathias Krauss , Sam Koblenski
- Applicant: Mathias Krauss , Sam Koblenski
- Applicant Address: DE Dresden
- Assignee: ZENTRUM MIKROELEKTRONIK DRESDEN AG
- Current Assignee: ZENTRUM MIKROELEKTRONIK DRESDEN AG
- Current Assignee Address: DE Dresden
- International Application: PCT/US10/20709 WO 20100112
- Main IPC: G01R31/3187
- IPC: G01R31/3187

Abstract:
Method and system are provided for evaluating linearity of a capacitive-to-digital converter (CDC) of a capacitive sensor integrated circuit chip. The evaluating employs multiple test capacitors, which may be on-chip with the CDC, and includes: obtaining capacitance values for the multiple test capacitors and parasitic capacitances of a first input A and a second input B to the capacitive-to-digital converter; applying the multiple test capacitors in multiple permutations to the first input A and the second input B, and for each of at least some permutations, determining an error between an expected output of the CDC using the obtained capacitance values and an actual measured output of the CDC; and determining linearity error for the CDC using the determined errors for the permutations of applying the multiple test capacitors to the first input A and the second input B of the CDC.
Public/Granted literature
- US08836359B2 Capacitive input test method Public/Granted day:2014-09-16
Information query
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