A method of fabricating an array substrate including forming a first metal layer; forming a gate insulating layer and an active layer; forming a second metal layer; forming a gate line, an etch-stopper and a gate electrode by patterning the first and second metal layers; forming an interlayer insulating layer including an opening, wherein the opening corresponds to the etch-stopper such that the opening is divided into first and second semiconductor contact holes respectively exposing both sides of the active layer; forming first and second ohmic contact layers, a source electrode, a drain electrode and a data line, the first and second ohmic contact layers respectively contacting both sides of the active layer through the first and second semiconductor contact holes; removing an exposed portion of the etch-stopper; and forming a pixel electrode contacting the drain electrode.