System and method for effectively detecting small delay defects is disclosed. The method first loads layout information of an integrated circuit. Then, the nets and paths of the integrated circuit are partitioned into two groups based upon their physical information. The physical information comprises the length of each path and net and the number of vias at each path and net. A timing-aware automatic test pattern generator is configured to generate test patterns for the first group having paths and nets susceptible to small delay defects. A traditional transition delay fault test pattern generator is configured to generate test patterns for the second group.