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发明申请
US20120119383A1 STACKED INTEGRATED CIRCUIT PACKAGE FABRICATION METHODS THAT USE VIAS FORMED AND FILLED AFTER STACKING, AND RELATED STACKED INTEGRATED CIRCUIT PACKAGE STRUCTURES 有权
堆叠集成电路包装制造方法，堆叠后形成和填充的堆叠集成电路，以及相关的堆叠集成电路封装结构

STACKED INTEGRATED CIRCUIT PACKAGE FABRICATION METHODS THAT USE VIAS FORMED AND FILLED AFTER STACKING, AND RELATED STACKED INTEGRATED CIRCUIT PACKAGE STRUCTURES
摘要：
Microelectronic packages are fabricated by stacking integrated circuits upon one another. Each integrated circuit includes a semiconductor layer having microelectronic devices and a wiring layer on the semiconductor layer having wiring that selectively interconnects the microelectronic devices. After stacking, a via is formed that extends through at least two of the integrated circuits that are stacked upon one another. Then, the via is filled with conductive material that selectively electrically contacts the wiring. Related microelectronic packages are also described.
摘要（中）：

微电子封装通过彼此堆叠集成电路制造。 每个集成电路包括具有微电子器件的半导体层和在半导体层上具有有选择性地互连微电子器件的布线的布线层。 在堆叠之后，形成延伸通过彼此堆叠的至少两个集成电路的通孔。 然后，通孔被选择性地电接触布线的导电材料填充。 还描述了相关微电子封装。

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