Invention Application
- Patent Title: SEMICONDUCTOR DEVICE, FABRICATING METHOD THEREOF AND SEMICONDUCTOR PACKAGE INCLUDING THE SEMICONDUCTOR DEVICE
- Patent Title (中): 半导体器件及其制造方法及其半导体器件包括半导体器件
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Application No.: US13235369Application Date: 2011-09-17
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Publication No.: US20120133048A1Publication Date: 2012-05-31
- Inventor: Ho-Jin LEE , Tae-Je CHO , Dong-Hyeon JANG , Ho-Geon SONG , Se-Young JEONG , Un-Byoung KANG , Min-Seung YOON
- Applicant: Ho-Jin LEE , Tae-Je CHO , Dong-Hyeon JANG , Ho-Geon SONG , Se-Young JEONG , Un-Byoung KANG , Min-Seung YOON
- Applicant Address: KR Gyeonggi-do
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Gyeonggi-do
- Priority: KR10-2010-0119757 20101129
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.
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