A check engine includes a plurality of comparators, each including a plurality of flash cells, where each of the plurality of comparators is configured to store at least one reference bit included in a set of reference bits, and includes an input for presenting at least one target bit included in a set of target bits. Each of the plurality of comparators is configured to produce an output representing a level of matching between the at least one target bit and the at least one reference bit. The check engine is configured such that the outputs of the plurality of comparators are combined to produce a combined output. The check engine is configured to determine that the set of target bits matches the set of reference bits based on the combined output of the plurality of comparators.