发明申请
US20120155495A1 PACKET ASSEMBLY MODULE FOR MULTI-CORE, MULTI-THREAD NETWORK PROCESSORS
有权
多核,多线程网络处理器的分组组件模块
- 专利标题: PACKET ASSEMBLY MODULE FOR MULTI-CORE, MULTI-THREAD NETWORK PROCESSORS
- 专利标题(中): 多核,多线程网络处理器的分组组件模块
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申请号: US13405053申请日: 2012-02-24
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公开(公告)号: US20120155495A1公开(公告)日: 2012-06-21
- 发明人: James T. Clee , Deepak Mital , Robert J. Munoz
- 申请人: James T. Clee , Deepak Mital , Robert J. Munoz
- 主分类号: H04J3/24
- IPC分类号: H04J3/24
摘要:
Described embodiments provide for processing received data packets into packet reassemblies for transmission as output packets of a network processor. A packet assembler determines an associated packet reassembly of data portions and enqueues an identifier for each data portion in an input queue corresponding to the packet reassembly associated with the data portion. A state data entry corresponding to each packet reassembly identifies whether the packet reassembly is actively processed by the packet assembler. Iteratively, until an eligible data portion is selected, the packet assembler selects a given data portion from a non-empty input queue for processing and determines if the selected data portion corresponds to a reassembly that is actively processed. If the reassembly is active, the packet assembler sets the selected data portion as ineligible for selection. Otherwise, the packet assembler selects the data portion for processing and modifies the packet reassembly based on the selected data portion.
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