发明申请
US20120164787A1 VACUUM WAFER LEVEL PACKAGING METHOD FOR MICRO ELECTRO MECHANICAL SYSTEM DEVICE
有权
用于微电子机械系统装置的真空水平包装方法
- 专利标题: VACUUM WAFER LEVEL PACKAGING METHOD FOR MICRO ELECTRO MECHANICAL SYSTEM DEVICE
- 专利标题(中): 用于微电子机械系统装置的真空水平包装方法
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申请号: US13309582申请日: 2011-12-02
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公开(公告)号: US20120164787A1公开(公告)日: 2012-06-28
- 发明人: Jong Tae Moon , Yong Sung Eom , Hyun-Cheol Bae
- 申请人: Jong Tae Moon , Yong Sung Eom , Hyun-Cheol Bae
- 申请人地址: KR Daejeon
- 专利权人: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
- 当前专利权人: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
- 当前专利权人地址: KR Daejeon
- 优先权: KR10-2010-0133515 20101223
- 主分类号: H01L21/60
- IPC分类号: H01L21/60
摘要:
Disclosed is a vacuum wafer level packaging method for a micro electro mechanical system device, including: forming a plurality of via holes on an upper wafer for protecting a micro electro mechanical system (MEMS) wafer; forming at least one metal layer on inner walls of the plurality of via holes and regions extended from the plurality of via holes; arranging and bonding the upper wafer and the MEMS wafer at atmospheric pressure; applying solder paste to the regions extended from the plurality of via holes; filling a solder in the plurality of via holes by increasing the temperature of a high-vacuum chamber to melt the solder paste; and changing the solder in the plurality of via holes to a solid state by lowering the temperature of the high-vacuum chamber.
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