发明申请
US20120210181A1 SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST
有权
用于系统级测试的扫描链的选择性周期性掩蔽
- 专利标题： SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST
- 专利标题（中）： 用于系统级测试的扫描链的选择性周期性掩蔽
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申请号： US13453929申请日： 2012-04-23
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公开(公告)号： US20120210181A1公开(公告)日： 2012-08-16
- 发明人: Janusz Rajski , Dariusz Czysz , Grzegorz Mrugalski , Nilanjan Mukherjee , Jerzy Tyszer
- 申请人： Janusz Rajski , Dariusz Czysz , Grzegorz Mrugalski , Nilanjan Mukherjee , Jerzy Tyszer
- 专利权人： Mentor Graphics Corporation
- 当前专利权人： Mentor Graphics Corporation
- 主分类号： G01R31/3177
- IPC分类号： G01R31/3177 ; G06F11/25
摘要：
Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.