发明申请
- 专利标题： METHOD OF FORMING AN INTEGRATED POWER DEVICE AND STRUCTURE
- 专利标题（中）： 形成集成电力设备和结构的方法
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申请号： US13458732申请日： 2012-04-27
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公开(公告)号： US20120211827A1公开(公告)日： 2012-08-23
- 发明人: Francine Y. Robb , Stephen P. Robb , Prasad Venkatraman , Zia Hossain
- 申请人： Francine Y. Robb , Stephen P. Robb , Prasad Venkatraman , Zia Hossain
- 主分类号： H01L29/78
- IPC分类号： H01L29/78 ; H01L21/336
摘要：
In one embodiment, a vertical power transistor is formed on a semiconductor substrate with other transistors. A portion of the semiconductor layer underlying the vertical power transistor is doped to provide a low on-resistance for the vertical power transistor.
公开/授权文献
- US08748262B2 Method of forming an integrated power device and structure 公开/授权日：2014-06-10
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