发明申请
US20120221614A1 Processor Pipeline which Implements Fused and Unfused Multiply-Add Instructions
有权
处理器管道,实现融合和未填充的乘法添加说明
- 专利标题: Processor Pipeline which Implements Fused and Unfused Multiply-Add Instructions
- 专利标题(中): 处理器管道,实现融合和未填充的乘法添加说明
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申请号: US13469212申请日: 2012-05-11
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公开(公告)号: US20120221614A1公开(公告)日: 2012-08-30
- 发明人: Jeffrey S. Brooks , Christopher H. Olson
- 申请人: Jeffrey S. Brooks , Christopher H. Olson
- 主分类号: G06F7/48
- IPC分类号: G06F7/48
摘要:
Implementing an unfused multiply-add instruction within a fused multiply-add pipeline. The system may include an aligner having an input for receiving an addition term, a multiplier tree having two inputs for receiving a first value and a second value for multiplication, and a first carry save adder (CSA), wherein the first CSA may receive partial products from the multiplier tree and an aligned addition term from the aligner. The system may include a fused/unfused multiply add (FUMA) block which may receive the first partial product, the second partial product, and the aligned addition term, wherein the first partial product and the second partial product are not truncated. The FUMA block may perform an unfused multiply add operation or a fused multiply add operation using the first partial product, the second partial product, and the aligned addition term, e.g., depending on an opcode or mode bit.
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