发明申请
- 专利标题: CHECKSUM VERIFICATION ACCELERATOR
- 专利标题(中): 检查验证加速器
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申请号: US13466940申请日: 2012-05-08
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公开(公告)号: US20120221928A1公开(公告)日: 2012-08-30
- 发明人: Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Jean Verplanken
- 申请人: Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Jean Verplanken
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 优先权: EP10306409.3 20101214
- 主分类号: H03M13/09
- IPC分类号: H03M13/09 ; G06F11/10
摘要:
Disclosed a method for validating a data packet by a network processor supporting a first, network protocol and a second network protocol and utilizing shared hardware. The network processor receives a data packet: identities a network packet protocol for the data packet; and processes the data packet according to the network packet protocol comprising: updating a first register with a first partial packet length specific to the first network protocol; updating a second register with a second partial packet length specific to the second network protocol; and updating a third register with a first checksum computed from fields independent of the network protocol. The method produces a second checksum utilizing a function that combines values from the first register, the second register, and the third register. The method validates the data packet by comparing the data packet checksum to the second checksum.
公开/授权文献
- US08726134B2 Checksum verification accelerator 公开/授权日:2014-05-13
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