A semiconductor memory device includes a memory cell array, a power source circuit, a sense amplifier, a control circuit, and a processor. The memory cell array includes a nonvolatile memory cell. The power source circuit includes a first register and generates a voltage. The sense amplifier includes a second register, reads from the memory cell and amplifies the read data. The control circuit includes a third register and controls operations of the power source circuit and the sense amplifier. The processor controls the operations of the power source circuit, the sense amplifier and the control circuit by giving an instruction to the first to third registers. The control circuit decodes the instruction received at the third register so as to control the power source circuit and the sense amplifier directly based on a result of decoding.