A stage of pipeline analog to digital converter (ADC) includes a multiplying digital to analog converter (MDAC) and a sub-analog to digital converter (sub-ADC). The sub-ADC includes a comparator and a random offset controller. The comparator is coupled to compare a first analog signal received by the stage with a reference signal. The random offset controller is coupled to the comparator to apply a random offset to an input of the comparator to randomly distribute errors by the sub-ADC in a digital output of the pipeline ADC.