发明申请
US20120264268A1 METHODS OF FORMING ELECTRICAL ISOLATION REGIONS BETWEEN GATE ELECTRODES
审中-公开
在门电极之间形成电隔离区的方法
- 专利标题: METHODS OF FORMING ELECTRICAL ISOLATION REGIONS BETWEEN GATE ELECTRODES
- 专利标题(中): 在门电极之间形成电隔离区的方法
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申请号: US13441124申请日: 2012-04-06
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公开(公告)号: US20120264268A1公开(公告)日: 2012-10-18
- 发明人: Ji-Hwon Lee
- 申请人: Ji-Hwon Lee
- 专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人: Samsung Electronics Co., Ltd.
- 优先权: KR10-2011-0034689 20110414
- 主分类号: H01L21/336
- IPC分类号: H01L21/336 ; H01L21/76 ; H01L21/02
摘要:
Methods of forming nonvolatile memory devices include forming first and second floating gate electrodes of first and second nonvolatile memory cells, respectively, at side-by-side locations on a substrate. The substrate is selectively etched to define a trench therein extending between the first and second floating gate electrodes. The trench is at least partially filled with a first electrical insulation pattern. An inorganic polysilazane-type spin-on-glass (SOG) layer is conformally deposited on the first and second floating gate electrodes and on the first electrical insulation pattern and then partially removed.