发明申请
US20120278771A1 Logic modification synthesis for high performance circuits 失效
高性能电路的逻辑修改综合

Logic modification synthesis for high performance circuits
摘要:
A method for IC modification is disclosed. The method recognizes an original HDL file prescribing an original logic, an original netlist incorporating the original logic, and a new HDL file prescribing a new logic. The new logic comprises desired logic changes relative to the original logic. If a signal is different between the new HDL file and the original HDL file the method adds a user hint to both the original HDL file and the new HDL file. Using the original HDL file, the original netlist, the new HDL file, and the user hints, the method synthesizes a delta netlist for inserting into the original netlist, whereupon this insertion the original netlist will incorporate the new logic.
公开/授权文献
信息查询
0/0