发明申请
- 专利标题: METHODS OF MODELING A TRANSISTOR AND APPARATUS USED THEREIN
- 专利标题(中): 用于建模晶体管的方法及其使用的装置
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申请号: US13371487申请日: 2012-02-13
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公开(公告)号: US20120297351A1公开(公告)日: 2012-11-22
- 发明人: Jaeheon SHIN , Woo-Seok Cheong , Chi-Sun Hwang , Sung Mook Chung
- 申请人: Jaeheon SHIN , Woo-Seok Cheong , Chi-Sun Hwang , Sung Mook Chung
- 申请人地址: KR Daejeon
- 专利权人: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
- 当前专利权人: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
- 当前专利权人地址: KR Daejeon
- 优先权: KR10-2011-0048064 20110520
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
Methods of modeling a transistor are provided. The method includes the steps of (a) extracting reference mobility values of a channel layer of a transistor including a gate electrode, a source region and a drain region using a reference gate voltage, a reference drain current and a reference drain voltage, (b) fitting a mobility function including model parameters on the reference mobility values to extract the model parameters, and (c) putting the extracted model parameters into a drain current modeling function to calculate a drain current flowing through the channel layer between the drain region and the source region under a bias condition defined by an arbitrary gate voltage applied to the gate electrode and an arbitrary drain voltage applied to the drain region. Related apparatuses are also provided.
公开/授权文献
- US08572546B2 Methods of modeling a transistor and apparatus used therein 公开/授权日:2013-10-29
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