Invention Application
US20120311399A1 MULTI-BIT ERROR CORRECTION METHOD AND APPARATUS BASED ON A BCH CODE AND MEMORY SYSTEM
审中-公开
基于BCH代码和存储器系统的多位错误校正方法和设备
- Patent Title: MULTI-BIT ERROR CORRECTION METHOD AND APPARATUS BASED ON A BCH CODE AND MEMORY SYSTEM
- Patent Title (中): 基于BCH代码和存储器系统的多位错误校正方法和设备
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Application No.: US13588700Application Date: 2012-08-17
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Publication No.: US20120311399A1Publication Date: 2012-12-06
- Inventor: Yufei LI , Yong LU , Ying WANG , Hao YANG
- Applicant: Yufei LI , Yong LU , Ying WANG , Hao YANG
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Priority: CN200910007392.3 20090223
- Main IPC: H03M13/29
- IPC: H03M13/29 ; G06F11/10

Abstract:
Exemplary embodiments for providing multi-bit error correction based on a BCH code are provided. In one such embodiment, the following operations are repeatedly performed, including shifting each bit of the BCH code rightward by 1 bit while filling the bit vacated due to the rightward shifting in the BCH code with 0, calculating syndrome values corresponding to the shifting of the BCH code, and determining a first error number in the BCH code under the shifting based on the syndrome values corresponding to the shifting of the BCH code. In the case where the first error number is not equal to 0, modified syndrome values are calculated corresponding to the shifting of the BCH code. The modified syndrome values are those corresponding to the case that the current rightmost bit of the BCH code under the shifting is changed to the inverse value. Additional operations are performed as described herein.
Public/Granted literature
- US09037953B2 Multi-bit error correction method and apparatus based on a BCH code and memory system Public/Granted day:2015-05-19
Information query
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